CONSTRUCTION PECULIARITIES OF TPC-DECODER SEPARATE BLOCKS ON THE BASE OF FPGA

  • Yaroslav Krainyk Chernomorsk Petro Mokhyla National University
  • Vladislav Perov Chernomorsk Petro Mokhyla National University
Keywords: decoder, unit, Turbo-Product-codes, PLIC

Abstract

The paper considers the problem, dealing with the construction of the certain blocks  for the  reconfigurable decoder of Turbo‑Product-codes. Principles of organization of the blocks   of minimal values position search in the input vector and universal shift unit were suggested, they enable to provide the reuse of the logic resources  of the programmable logic microcircuits for processing of the codes of various structure. Principles of blocks organization are suitable for usage both in  specialized microcircuits and in  the programmable logic integrated circuits (PLIC), but the emphasis is made on the latter due to their universality and possibility of the multiple change of configuration structure. The developed searching unit uses in its structure two types of simple elements and on their base allocates values which are minimal. The structure, enabling to perform the search of the preset amount of the minimal values is proposed. In its turn, universal shift unit provides necessary relocations  in the input or output vector of values, so that they can be written in the memory module or sent to the processing module. As a result of using this unit the parallel access to the values in the memory is provided, this increases considerably the rate of the decoding process. Besides, the unit is oriented on the work with the codes of different length and performs the values shift during minimal number of operation frequency cycles. Accordingly, irrespective of the code, used in the process of decoding, values shift will be performed during one and the same unit of time. In accordance with the principles, suggested in the paper, corresponding units are developed by means of the language of circuit engineering description VHDL. Simulation of the developed units operation is performed, it proved the correctness of their operation. These units in the decoder Turbo-Product-codes enable to improve the universality of the decoder, providing high carrying capacity.

Downloads

Download data is not yet available.

Author Biographies

Yaroslav Krainyk, Chernomorsk Petro Mokhyla National University

Cand. Sc. (Eng.), Doctoral fellow, Senior Lecturer with the Department of Computer Engineering

Vladislav Perov, Chernomorsk Petro Mokhyla National University

Post Graduate with the Department of Compute Engineering

Published
2018-03-30
How to Cite
[1]
Y. Krainyk and V. Perov, “CONSTRUCTION PECULIARITIES OF TPC-DECODER SEPARATE BLOCKS ON THE BASE OF FPGA”, SWVNTU, no. 1, Mar. 2018.
Section
Information Technologies and Computer Engineering